a. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly to on-chip inductor components.
b. Background of Invention
Many communication systems may be realized on a single chip. With an increased demand for personal mobile communications, integrated semiconductor devices such as complementary metal oxide semiconductor (CMOS) devices may, for example, include voltage controlled oscillators (VCO), low noise amplifiers (LNA), tuned radio receiver circuits, or power amplifiers (PA). Each of these tuned radio receiver circuits, VCO, LNA, and PA circuits may, however, require on-chip inductor components in their circuit designs. Thus, there may be a need for high quality on-chip inductor devices.
Several design considerations associated with forming on-chip inductor components may, for example, include quality factor (i.e., Q-factor), self-resonance frequency (fSR), and cost considerations impacted by the area occupied by the formed on-chip inductor. Accordingly, for example, a CMOS radio frequency (RF) circuit design may benefit from, among other things, one or more on-chip inductors having a high Q-factor, a small occupied chip area, and a high fSR value.
The self-resonance frequency (fSR) of an inductor may be given by the following equation:
            f      SR        =          1              2        ⁢                                  ⁢        π        ⁢                  LC                      ,where L is the inductance value of the inductor and C may be the capacitance value associated with the inductor coil's inter-winding capacitance, the inductor coil's interlayer capacitance, and the inductor coil's ground plane (i.e., chip substrate) to coil capacitance. As deduced from the above relationship, a reduction in capacitance C may desirably increase the self-resonance frequency (fSR) of an inductor. One method of reducing the coil's ground plane to coil capacitance (i.e., metal to substrate capacitance) and, therefore, C value, is by using a high-resistivity semiconductor substrate such as a silicon-on-insulator (SOI) substrate. By having a high resistivity substrate (e.g., >50 Ω-cm), the effect of the coil's metal (i.e., coil tracks) to substrate capacitance is diminished, which in turn may increase the self-resonance frequency (fSR) of the inductor.
The Q-factor of an inductor may be given by the equation:
      Q    =                  ω        ⁢                                  ⁢        L            R        ,where ω is the angular frequency, L is the inductance value of the inductor, and R is the resistance of the coil. As deduced from the above relationship, a reduction in coil resistance may lead to a desirable increase in the inductor's Q-factor. For example, in an on-chip inductor, by increasing the turn-width (i.e., coil track width) of the coil, R may be reduced in favor of increasing the inductors Q-factor to a desired value. In radio communication applications, the Q-factor value is set to the operating frequency of the communication circuit. For example, if a radio receiver is required to operate at 2 GHz, the performance of the receiver circuit may be optimized by designing the inductor to have a peak Q frequency value of about 2 GHz. The self-resonance frequency (fSR) and Q-factor of an inductor are directly related in the sense that by increasing fSR, peak Q is also increased.
FIG. 1 shows a conventional on-chip stacked inductor 100, as known in the art. The depicted on-chip stacked inductor 100 may be fabricated on, for example, two metal layers 102, 104 corresponding to the back end of the line (BEOL) region of a semiconductor device. A first spiral structure 106 (i.e., a coil) is formed in metal layer 104, while a second spiral structure 108 (i.e., a coil) is formed in metal layer 102. The first spiral structure 106 is electrically coupled to the second spiral structure 108 by via 109, whereby the lower portion of the via 110a connects the first spiral structure 106 to the second spiral structure 108 by means of the upper portion of the via 110b. 
In operation, as illustrated, current may flow along the direction of the arrows from input 112 of the second spiral structure 108 to output 114 of the first spiral structure 106. As such, current entering at input 112 flows in a counter-clockwise direction from the outer-most-spiral track 116 to the inner-most-spiral track 118 of the second spiral structure 108. At the end of the inner-most-spiral track 118, current flows into the upper portion of the via 110b and out of the lower portion of the via 110a. From the lower portion of the via 110a, the current continues to flow in a counter-clockwise direction from the inner-most-spiral track 120 to output 114 of the outer-most-spiral track 122 of first spiral structure 106. The positive mutual inductive coupling between the first spiral 106 and second spiral 108 leads to a total inductance greater than the simple sum of the inductances of the two spirals taken by themselves. For example, a two layer spiral may experience as much as four times the inductance of the two layers taken separately and summed.
The depicted on-chip stacked inductor 100 structure exhibits an increased interlayer capacitance between the metal tracks of first spiral 106 and second spiral 108. This increased capacitance contributes towards reducing both the Q-factor and self-resonance frequency (fSR) of on-chip stacked inductor 100. Thus, it may, among other things, be advantageous to provide one or more on-chip inductor structures capable of having an increased Q-factor and self-resonance frequency (fSR), while maintaining a reduced footprint (i.e., smaller occupied area) with respect to the metal layers of the BEOL region of a semiconductor device.